Using four 6AS7 tubes per channel is not as arbitrary as it may seem. My idea was that that a stereo amplifier could be built that held eight 6AS7 tubes, with all eight heater elements stringed up in series and placed across the -50V power-supply rail, each heater getting 6.25Vdc.

Note that no phase splitter is required in this design, as the P-channel MOSFET and 6AS7 output triodes see the same signal phase; indeed, the same input signal. This would make the input stage far easier to design. A near infinite number of possible input stages could be devised. One possible design would be the Aikido Cascade circuit.

The above circuit only delivers a gain of about 56, so no negative feedback loop could be employed, bridging output to input. By switching to a 12DW7/ECC832/7247 dissimilar, dual-triode tube, we can get a gain closer to 140 and still enjoy an excellent PSSR figure. The 12AX7-based input stage leaks a third of the B+ ripple in phase to 12AU7's grid, whereupon the 12AU7's inverting gain roughly equals negative three, thereby nulling the power-supply noise that the output, as 1 - (0.33 x 3) = 0. Magic to most. Simple math for those in the know.*

On the other hand, an Aikido Cascode could easily produce enough signal gain to drive a negative feedback loop.

A 6DJ8 input tube and an ECC99 (or 12BH7 or 5687) output would do the job quite well.

MOSFETs in Parallel vs in Series
Note how two P-channel MOSFETs were used in series in the above hybrid output stage. Why did I use different types and why did I place them in series, rather than in parallel? Good questions. Another good question would be, Why did I use two MOSFETs rather than just one? Although they are rated for over 100W, the MOSFETs cannot tolerate all that much heat. In the hybrid design above, I assumed an idle current of 0.4A, which against the -50V power-supply rail would generate 20W of heat from a single MOSFET, which isn't too bad with a huge heatsink and cold room; but with a smaller heatsink and a hot summer day, I worry. With two MOSFETs, I worry half as much.

The BUZ906P is a lateral MOSFET that is both rare and expensive, whereas the IRFP9240 is both common and cheap. Since the BUZ906 is in control of the current flow through both MOSFETs, we can save by using the two different MOSFETs in series. On the other hand, if they had been placed in parallel, both would have to be the same high-quality lateral types, preferably matched devices. In addition, we would double the input capacitance, not a good idea, as the MOSFETs already present a heavy capacitance load. Sophos utm appliance.

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Okay, so let's place the MOSFETs in series. Are we done? No. We still face a potential problem, which the bomb symbols signifies: limited power output. Don't see how that is possible? Well, look at the following schematic and tell me what's wrong.

Mosfet In Series And Parallel Equation

The two-resistor voltage dividers evenly split the rail voltages, true enough. But do the MOSFETs in series evenly split the rail voltages and what is the maximum voltage output swing that the above output stage can muster? The answers are that the MOSFETs do not evenly share the rail voltage and that output can only swing up about 40Vpk, as two-resistor voltage dividers cannot deliver an output voltage greater than the rail voltage. A big problem. The easy and inadequate solution is to alter the voltage divider resistor values, so the each MOSFET gets an even share of rail voltage.

Looks great, so why is it inadequate? The problem of equal dissipation was solved, but not the problem of unnecessarily limited output swing. To solve this second problem, the following variation is needed.

The 8-volt zener diodes were chosen to equal twice the gate-to-source voltage of the topmost and bottommost MOSFETs. The large-valued electrolytic bypass capacitors will charge up to 8Vdc; and when the crescendo hits, they will be able to swing the pair of two-resistor voltage dividers output voltages beyond the power-supply rail voltage, which will allow the MOSFETs to swinger bigger output voltages. This workaround works well with music reproduction, but will begin to fail at steady sine waves, as the electrolytic capacitors will begin to loose some of their charge.

* Well, Actually
The math is not nearly as simple as that. But this is fine first approximation. And if we had been dealing with pentodes, it would be close enough. Triodes, on the other hand, exhibit a relatively low plate resistance (rp), so the math gets thicker, much thicker. The procedure is to perform a bunch of iterative steps, starting with that first approximation, that will finally arrive at the true power-supply null. Here is a 6DJ8-based Aikido Cascade circuit:

The second grounded-cathode gain stage develops a gain of on 2.5, not the 3 that the first approximation predicted. The reason it is less than 3 is that 100% of the power-supply noise did not appear at the output, only 76% did, so less inverting gain was needed to null the noise. Additionally, the first stage does divide the DC B+ voltage to a third, but not the AC voltages riding on the B+ connection; instead, it leaks 30% of the ripple, not 33%. By the way, the PSRR is extremely fine, coming in at about -60dB in SPICE simulations. The gain is a bit too low for use as an OTL frontend, as it is only about 54 (+34.6dB), but this circuit might make a fine tube microphone preamp. Do not get the idea that since the circuit displays a fine PSRR you can ignore the power supply altogether; you cannot. The Aikido Cascade circuit makes you work lighter, but you still have some work to do.

Next Time
More hybrid designs and, if I can finish the user guides, news of new GlassWare PCBs and kits.

For those of you who still have old computers running Windows XP (32-bit) or any other Windows 32-bit OS, I have setup the download availability of my old old standards: Tube CAD, SE Amp CAD, and Audio Gadgets. The downloads are at the GlassWare-Yahoo store and the price is only $9.95 for each program.

So many have asked that I had to do it.

WARNING: THESE THREE PROGRAMS WILL NOT RUN UNDER VISTA 64-Bit or WINDOWS 7 & 8 or any other 64-bit OS.

I do plan on remaking all of these programs into 64-bit versions, but it will be a huge ordeal, as programming requires vast chunks of noise-free time, something very rare with children running about. Ideally, I would love to come out with versions that run on iPads and Android-OS tablets.

//JRB

Series

The following slides are covered in the YouTube video above.
Several visitors to this website have tried to connect power MOSFET transistors in parallel in order to switch a higher power load. Here I'll explore that issue and why problems may arise.

Fig. 1 N-channel MOSFETs connected in parallel.

Fig.1 illustrates 4 n-channel MOSFETs connected in parallel. At issue is Rg the gate bleeder resistor. Due to MOSFET construction with a very thin dielectric insulator between gate-source can create considerable capacitance. Rg is designed to bleed of the charge on the gate when turned on at assure turn off.
The problem is when MOSFETs are connected in parallel the capacitance is multiplied and that is where the trouble begins. Going by the specification sheet one can Cgs. Note the left side of Fig. 1 on how the MOSFET is constructed.

Fig. 2 Construction of N-channel MOSFET.

Fig. 2 illustrates the construction of a typical n-channel MOSFET. A positive charge on the gate electrode draws negative charges to the gate creating a conductive pathway. This would seem to create even more capacitance as the insulator separates the gate from the conductive channel. A capacitor after all is two conductors separated by an insulator.

Fig. 3 Effects of stray capacitance in power MOSFET switching.

Fig. 3 taken from International Rectifier shows the problems of stray capacitance and inductance with a MOSFET. This can easily distort the drive signal creating noise and switching problems.

Fig. 4 Input capacitance distorts square wave drive signal to MOSFET.

The result is a nice clean digital pulse from say an Arduino microcontroller has a lagging turn on and lagging turn off. This charge curve is common in capacitive-resistive circuits.
Trying to switch on-off multiple MOSFET at one time becomes a challenge. Let's look more closely at how to address possible solutions.
Update Dec. 2019. Many micro-controllers today are using 3.3-volt Vcc. This is also true of Raspberry Pi. I found two MOSFETs that work at 3.3-volts.
The IRFZ44N is an N-channel device rated at 55V and RDS(on) resistance of 0.032 Ohms max. The other is a P-channel device rated at 55V and a RDS(on) of 0.02 Ohms max.
See the following spec sheets:
Also see Test Power MOSFET Transistors, Results, Observations

Tricare copay 2020. Fig. 5 Charge curve for 3-volt MOSFET square wave drive pulse.

Many hobbyists use a 3-volt microcontroller or in the case of Raspberry Pi 3-volt IO is the norm. Gate-source capacitance becomes a real problem at lower voltages in the reliable switching on-off of multiple paralleled MOSFETs.
Let's note a charge curve that T (for time) is C * R. The charge curve is not linear. The fastest voltage rise is the first period T, then the rates greatly slows down. 5 times T is considered fully charged.
The exact opposite for turn-off or discharge.
Some MOSFETs will turn on at 3-volts, but many that I've tested fully turn on from 3.5 to 4.3 volts. This is further compounded that in the real world every MOSFET is not 100% identical even if the same part number.
As Fig. 5 at 3-volts it will take 3T to come up near 3 volts to turn on a MOSFET. More MOSFETs more capacitance, longer time period for T.

Fig. 6 Charge curve for 5-volt MOSFET square wave drive pulse.

In Fig.6 with 5-volts 1T produces 3.6V turning on most MOSFETs. Somewhere between 1T and 2T assures most MOSFETs such as the IRF630 will turn fully on.

Fig. 7 Charge curve for 12-volt MOSFET square wave drive pulse.

Fig. 7 illustrates the use of a 12-volt pulse. 1/2 T will switch on all MOSFETs. This may not be so good for turn off as the higher voltage discharge may delay turn off.

Fig. 8 MOSFET based driver circuit.

While we can't reduce Cgs other than using MOSFETs with a lower Cgs, the best solution is to reduce R. The circuit in Fig. 8 can be a solution.
A HIGH input will switch on Q2 providing a fast low-resistance pulse providing the rush of current need to switch on the 4 MOSFETs. A low input turn on Q1 providing a very low resistance discharge path.

Fig. 9 Parallel MOSFETs configuration 1.

Fig. 9 illustrates parallel MOSFETs with gates connected together and a single charge/discharge resistor. The diode suppresses noise generated as current rushes through the resistor.

Fig. 10 Parallel MOSFETs with individual gate resistors.

Fig. 10 illustrates a resistor on each individual MOSFET gate. With either Fig. 9 or 10 include the 10K resistor is included so the MOSFETs are assured to be turned off at power up.
Have fun.